 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| general description the MAX1497/max1499 low-power, 3.5- and 4.5-digit, analog-to-digital converters (adcs) with integrated light- emitting diode (led) drivers operate from a single 2.7v to 5.25v power supply. they include an internal refer- ence, a high-accuracy on-chip oscillator, and a multi- plexed led display driver. an internal charge pump generates the negative supply needed to power the integrated input buffers for single-supply operation. the adc is configurable for either a ?v or ?00mv input range and it outputs its conversion results to an led and/or to a microcontroller (?). ? communication is possible through an spi -/qspi -/microwire - compatible serial interface. the MAX1497 is a 3.5-digit (?999 count) device and the max1499 is a 4.5-digit (?9,999 count) device. the MAX1497/max1499 do not require external preci- sion integrating capacitors, autozero capacitors, crystal oscillators, charge pumps, or other circuitry required with dual-slope adcs (commonly used in panel meter circuits). these devices also feature on-chip buffers for the dif- ferential signal and reference inputs, allowing direct interface with high-impedance signal sources. in addi- tion, they use continuous internal offset-calibration and offer >100db rejection of 50hz and 60hz line noise. other features include data hold and peak detection, overrange and underrange detection, and a user-pro- grammable low-battery monitor. the max1499 is available in a 32-pin, 7mm ? 7mm tqfp package and the MAX1497 is available in 28-pin ssop and 28-pin pdip packages. all devices in this family operate over the -40? to +85? extended tem- perature range. applications digital panel meters hand-held meters digital voltmeters digital multimeters features high resolution max1499: 4.5 digits (?9,999 count) MAX1497: 3.5 digits (?999 count) sigma-delta adc architecture no integrating capacitors required no autozeroing capacitors required >100db of simultaneous 50hz and 60hz rejection operate from a single 2.7v or 5.25v supply selectable input range of ?00mv or ?v selectable voltage reference: internal 2.048v or external internal high-accuracy oscillator needs no external components automatic offset calibration low power (exclude led driver current) maximum 664? operating current maximum 268ma shutdown current small 32-pin, 7mm x 7mm tqfp package (4.5 digits), 28-pin ssop package (3.5 digits) also available in a pdip package (3.5 digits) multiplexed led drivers resistor-programmable segment current spi-/qspi-/microwire-compatible serial interface extended temperature range (-40? to +85?) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ________________________________________________________________ maxim integrated products 1 ordering information 19-3054; rev 0; 11/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package resolution (digits) MAX1497 eai* -40 c to +85 c 28 ssop 3.5 MAX1497epi -40 c to +85 c 28 pdip 3.5 max1499 ecj* -40 c to +85 c 32 tqfp 4.5 pin configurations appear at end of data sheet. * future product?ontact factory for availability. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to gnd (max1499).........................................-0.3v to +6v dv dd to gnd (max1499) ........................................-0.3v to +6v ain+, ain- to gnd (max1499) ...........vneg to (av dd to +0.3v) ref+, ref- to gnd (max1499) ......... vneg to (av dd to +0.3v) lowbatt to gnd (max1499) ................-0.3v to (av dd + 0.3v) clk, eoc , cs , din, sclk, dout to gnd (max1499) .......................-0.3v to (dv dd + 0.3v) vneg to gnd (max1499) .......................-2.6v to (av dd + 0.3v) led_en to gnd (max1499)....................-0.3v to (dv dd + 0.3v) iset to gnd (max1499)..........................-0.3v to (av dd + 0.3v) v dd to gnd (MAX1497) ...........................................-0.3v to +6v ain+, ain- to gnd (MAX1497)..............vneg to (v dd to +0.3v) ref+, ref- to gnd (MAX1497) ........... vneg to (v dd to +0.3v) clk, eoc , cs , din, sclk, dout to gnd (MAX1497)..........................-0.3v to (v dd + 0.3v) vneg to gnd (MAX1497)..........................-2.6v to (v dd + 0.3v) iset to gnd (MAX1497) ............................-0.3v to (v dd + 0.3v) vled to gled ..........................................................-0.3v to +6v gled to gnd ........................................................-0.3v to +0.3v seg_ to gled..........................................-0.3v to (vled + 0.3v) dig_ to gled ..........................................-0.3v to (vled + 0.3v) dig_ sink current .............................................................300ma dig_ source current...........................................................50ma seg_ sink current ..............................................................50ma seg_ source current..........................................................50ma maximum current input into any other pin ........................50ma continuous power dissipation (t a = +70 c) 32-pin tqfp (derate 20.7mw/ c above +70 c).....1652.9mw 28-pin ssop (derate 9.5mw/ c above +70 c) ...........762mw 28-pin pdip (derate 14.3mw/ c above +70 c)......1142.9mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (av dd = dv dd = v dd = +2.7v to +5.25v, gnd = 0, gled = 0, v led = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference) c ref+ = c ref- = 0.1f, c vneg = 0.1f. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units dc accuracy max1499 -19,999 +19,999 noise-free resolution MAX1497 -1999 +1999 count 2.000v range 1 integral nonlinearity (note 1) inl 200mv range 1 count range change ratio (v ain+ - v ain- = 0.100v) on 200mv range (v ain+ - v ain- = 0.100v) on 2.0v range 10:1 ratio rollover error v ain+ - v ain- = full scale v ain- - v ain+ = full scale 1 count output noise 10 v p-p offset error (zero input reading) offset v in = 0 (note 2) -0 0 reading gain error (note 3) -0.5 +0.5 %fsr offset drift (zero reading drift) v in = 0 (note 4) 0.1 v/ c gain drift 1 ppm/ c input conversion rate external-clock frequency 4.9152 mhz external-clock duty cycle 40 60 % internal clock 5 conversion rate external clock, f clk = 4.9152mhz 5 hz MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units analog inputs (ain+, ain-) (bypass to gnd with 0.1f or greater capacitors) range bit = 0 -2.0 +2.0 ain input voltage range (note 5) range bit = 1 -0.2 +0.2 ain absolute input voltage range to gnd -2.2 +2.2 v internal clock mode, 50hz and 60hz 2% 100 normal-mode 50hz and 60hz rejection (simultaneously) external clock mode, 50hz and 60hz 2%, f clk = 4.9152mhz 120 db common-mode 50hz and 60hz rejection (simultaneously) cmr for 50hz and 60hz 2%, r source < 10k ? 150 db common-mode rejection cmr at dc 100 db input leakage current 10 na input capacitance 10 pf average dynamic input current (note 6) -20 +20 na low-battery voltage monitor (lowbatt) (max1499 only) lowbatt tripthreshold 2.048 v lowbatt leakage current 10 pa hysteresis 20 mv internal reference (ref- = gnd, intref bit = 1) (bypass ref+ to gnd with a 4.7f capacitor) ref output voltage v ref av dd = v dd = 5v 2.007 2.048 2.089 v ref output short-circuit current 1ma ref output temperature coefficient tc vref av dd = v dd = 5v 40 ppm/ c load regulation i source = 0 to 300a, i sink = 0 to 30a 6 mv/a line regulation 50 v/v 0.1hz to 10hz 25 noise voltage 10hz to 10khz 400 v p-p external reference (intref bit = 0) (bypass ref+ and ref- to gnd with 0.1f or greater capacitors) ref input voltage differential (v ref+ - v ref- ) 2.048 absolute ref+, ref- input voltage to gnd -2.2 +2.2 v internal clock mode, 50hz and 60hz 2% 100 normal-mode 50hz and 60hz rejection (simultaneously) external clock mode, 50hz and 60hz 2%, f clk = 4.9152mhz 120 db common-mode 50hz and 60hz rejection (simultaneously) cmr for 50hz and 60hz 2%, r source < 10k ? 150 db common-mode rejection cmr at dc 100 db input leakage current 10 na electrical characteristics (continued) (av dd = dv dd = v dd = +2.7v to +5.25v, gnd = 0, gled = 0, v led = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference) c ref+ = c ref- = 0.1f, c vneg = 0.1f. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units input capacitance 10 pf average dynamic input current (note 6) -20 +20 na charge pump output voltage vneg c vneg = 0.1f -2.60 -2.42 -2.30 v digital inputs (sclk, din, cs , clk) input current i in v in = 0 or dv dd = v dd -10 +10 a max1499 0.3 x dv dd input low voltage v inl MAX1497 0.3 x v dd v max1499 0.7 x dv dd input high voltage v inh MAX1497 0.7 x v dd v input hysteresis v hys dv dd = v dd = 3.0v 200 mv digital outputs (dout, eoc ) output low voltage v ol i sink = 1ma 0.4 v i source = 200a, m ax 1499 0.8 x dv dd output high voltage v oh i source = 200a, m ax 1497 0.8 x v dd v tri-state leakage current i l dout only -1 +1 a tri-state output capacitance c out dout only 15 pf power supply (note 10) v dd voltage v dd MAX1497 2.70 5.25 v av dd voltage av dd max1499 2.70 5.25 v dv dd voltage dv dd max1499 2.70 5.25 v power-supply rejection v dd psrr (note 7) 80 db power-supply rejection av dd psrr a (note 7) 80 db power-supply rejection dv dd psrr d (note 7) 100 db v dd = 5.25v 664 744 v dd = 3.3v 618 663 v dd current (notes 8, 9) i vdd standby mode 268 325 a av dd = 5.25v 640 av dd = 3.3v 600 av dd current (notes 8, 9) i avdd standby mode 305 a electrical characteristics (continued) (av dd = dv dd = v dd = +2.7v to +5.25v, gnd = 0, gled = 0, v led = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference) c ref+ = c ref- = 0.1f, c vneg = 0.1f. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units dv dd = 5v 320 dv dd = 3.3v 180 dv dd current (notes 8, 9) i dvdd standby mode 20 a led drivers bias current from av dd or v dd 120 a led drivers (table 6) led supply voltage v led 2.70 5.25 v led shutdown supply current i shdn led driver shutdown mode 10 a led supply current i led seven segments and decimal point on, r iset = 25k ? 176 ma max1499 512 display scan rate f osc MAX1497 640 hz segment current slew rate ? i seg / ? t 25 ma/s dig_ voltage low v dig i dig_ = 176ma 0.178 0.190 v segment drive source current matching ? i seg 3 10 % segment drive source current i seg v led - v seg = 0.6v, r iset = 25k ? 18.0 21.5 25.5 ma interdigit blanking time 4s electrical characteristics (continued) (av dd = dv dd = v dd = +2.7v to +5.25v, gnd = 0, gled = 0, v led = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference) c ref+ = c ref- = 0.1f, c vneg = 0.1f. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 6 _______________________________________________________________________________________ timing characteristics (notes 11, 12, figure 8) (av dd = dv dd = v dd = +2.7v to +5.25v, gnd = 0, gled = 0, v led = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference) c ref+ = c ref- = 0.1f, c vneg = 0.1f. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units sclk operating frequency f sclk 0 4.2 mhz sclk pulse-width high t ch 100 ns sclk pulse-width low t cl 100 ns din to sclk setup t ds 50 ns din to sclk hold t dh 0ns cs fall to sclk rise setup t css 50 ns sclk rise to cs rise hold t csh 0ns sclk fall to dout valid t do c load = 50pf, figures 13, 14 120 ns cs rise to dout disable t tr c load = 50pf, figures 13, 14 120 ns cs fall to dout enable t dv c load = 50pf, figures 13, 14 120 ns note 1: integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and offset error. note 2: offset calibrated. see offset_cal1 and offset_cal2 (max1499 only) in the on-chip registers section. note 3: offset nulled. note 4: offset drift error is eliminated by recalibration at the new temperature. note 5: the input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pa ir. note 6: v ain + or v ain - = -2.2v to +2.2v. v ref + or v ref - = -2.2v to +2.2v. all input structures are identical. production tested on ain+ and ref+ only. note 7: measured at dc by changing the power-supply voltage from 2.7v to 5.25v and measuring the effect on the conversion error with external reference. psrr at 50hz and 60hz exceeds 120db with filter notches at 50hz and 60hz (figure 2). note 8: clk and sclk are disabled. note 9: led drivers are disabled. note 10: power-supply currents are measured with all digital inputs at either gnd, dv dd , or v dd and with the device in internal-clock mode. note 11: all input signals are specified with t rise = t fall = 5ns (10% to 90% of dv dd ) and are timed from a voltage level of 50% of dv dd , unless otherwise noted. note 12: see the serial-interface timing diagrams. MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface _______________________________________________________________________________________ 7 typical operating characteristics (av dd = dv dd = v dd = +2.7v to +5.25v, v led = +2.7v to +5.25v, gnd = 0, gled = 0, external reference mode, ref+ = 2.048v, ref- = gnd, c ref+ = c ref- = 0.1f, range bit = 1, internal clock mode, c vneg = 0.1f. t a = +25 c, unless otherwise noted.) supply current vs. supply voltage (max1499) MAX1497/99 toc01 supply voltage (v) supply current ( a) 4.75 4.25 3.75 3.25 100 200 300 400 500 600 700 0 2.75 5.25 analog supply digital supply supply current vs. supply voltage (MAX1497) MAX1497/99 toc02 supply voltage (v) supply current ( a) 4.74 4.23 3.72 3.21 450 500 550 600 650 700 400 2.70 5.25 supply current vs. temperature (max1499) MAX1497/99 toc03 temperature ( c) supply current ( a) 60 50 40 30 20 10 100 200 300 400 500 600 700 0 070 analog supply digital supply supply current vs. temperature (MAX1497) MAX1497/99 toc04 temperature ( c) supply current ( a) 60 35 -15 10 610 640 630 620 650 660 670 680 690 700 600 -40 85 shutdown current vs. temperature (max1499) MAX1497/99 toc05 temperature ( c) shutdown current ( a) 60 50 40 30 20 10 50 100 150 200 250 300 0 070 analog supply digital supply shutdown current vs. supply voltage (max1499) MAX1497/99 toc07 supply voltage (v) shutdown current ( a) 4.75 4.25 3.75 3.25 50 100 150 200 250 300 0 2.75 5.25 analog supply digital supply shutdown current vs. supply voltage (MAX1497) MAX1497/99 toc08 supply voltage (v) shutdown current ( a) 4.74 4.23 3.72 3.21 50 150 100 200 250 300 350 0 2.70 5.25 max1499 offset error vs. supply voltage MAX1497/99 toc09 supply voltage (v) offset error (lsb) 4.75 4.25 3.75 3.25 -0.11 -0.06 -0.01 0.04 0.09 0.14 0.19 -0.16 2.75 5.25 shutdown current vs. temperature (MAX1497) MAX1497/99 toc06 temperature ( c) shutdown current ( a) 60 35 -15 10 50 150 100 200 250 300 350 0 -40 85 internal reference voltage vs. temperature MAX1497/99 toc16 temperature ( c) reference voltage (v) 60 50 40 30 20 10 2.046 2.045 2.047 2.049 2.048 2.051 2.050 2.053 2.052 2.054 2.044 070 internal reference voltage vs. analog supply voltage MAX1497/99 toc17 supply voltage (v) reference voltage (v) 4.75 4.25 3.75 3.25 2.045 2.046 2.047 2.048 2.049 2.050 2.044 2.75 5.25 MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 8 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = v dd = +2.7v to +5.25v, v led = +2.7v to +5.25v, gnd = 0, gled = 0, external reference mode, ref+ = 2.048v, ref- = gnd, c ref+ = c ref- = 0.1f, range bit = 1, internal clock mode, c vneg = 0.1f. t a = +25 c, unless otherwise noted.) max1499 offset error vs. temperature MAX1497/99 toc10 temperature ( c) offset error (lsb) 60 50 10 20 30 40 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 -0.2 070 max1499 gain error vs. supply voltage MAX1497/99 toc11 supply voltage (v) gain error (% full scale) 4.75 4.25 3.25 3.75 -0.08 -0.04 -0.06 -0.02 0 0.02 0.04 0.06 0.08 -0.10 2.75 5.25 max1499 gain error vs. temperature MAX1497/99 toc12 temperature ( c) gain error (% full scale) 60 50 30 40 20 10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 -0.10 070 max1499 ( 200mv input range) inl vs. output code MAX1497/99 toc13 output code inl (counts) 10,000 0 -10,000 -0.5 0 0.5 1.0 -1.0 -20,000 20,000 max1499 ( 2v input range) inl vs. output code MAX1497/99 toc14 output code inl (counts) 10,000 0 -10,000 -0.5 0 0.5 1.0 -1.0 -20,000 20,000 noise distribution MAX1497/99 toc15 noise (lsb) percentage of units (%) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 5 10 15 20 25 0 -0.2 data output rate vs. temperature MAX1497/99 toc18 temperature ( c) data output rate (hz) 60 35 -15 10 4.92 4.98 4.96 4.94 5.00 5.02 5.04 5.06 5.08 5.10 4.90 -40 85 MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface _______________________________________________________________________________________ 9 typical operating characteristics (continued) (av dd = dv dd = v dd = +2.7v to +5.25v, v led = +2.7v to +5.25v, gnd = 0, gled = 0, external reference mode, ref+ = 2.048v, ref- = gnd, c ref+ = c ref- = 0.1f, range bit = 1, internal clock mode, c vneg = 0.1f. t a = +25 c, unless otherwise noted.) data output rate vs. supply voltage MAX1497/99 toc19 supply voltage (v) data output rate (hz) 4.74 4.23 3.21 3.72 4.995 4.990 4.985 5.000 5.005 5.010 5.015 5.020 4.980 2.70 5.25 offset error vs. common-mode voltage MAX1497/99 toc20 common-mode voltage (v) offset error (lsb) 1.5 1.0 -1.5 -1.0 -0.5 0 0.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 -2.0 2.0 segment current vs. supply voltage MAX1497/99 toc23 supply voltage (v) segment current ( a) 4.74 4.23 3.72 3.21 5 10 15 20 25 30 0 2.70 5.25 r iset = 25k ? v neg startup scope shot MAX1497/99 toc21 20ms/div 2v/div 1v/div v dd v neg charge-pump output voltage vs. analog supply voltage MAX1497/99 toc22 supply voltage (v) v neg voltage (v) 4.75 4.25 3.75 3.25 -2.48 -2.46 -2.44 -2.42 -2.40 -2.50 2.75 5.25 MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 10 ______________________________________________________________________________________ pin description pin MAX1497 max1499 name function 1 31 vneg -2.5v charge-pump voltage-output. connect a 0.1f capacitor to gnd. 2 32 ref- negative reference voltage input. for internal reference operation, connect ref- to gnd. for external reference operation, bypass ref- to gnd with a 0.1f capacitor and set v ref- from -2.2v to +2.2v, provided v ref+ > v ref- . 3 1 ref+ positive reference voltage input. for internal reference operation, connect a 4.7f capacitor from ref+ to gnd. for external reference operation, bypass ref+ to gnd with a 0.1f capacitor and set v ref+ from -2.2v to +2.2v, provided v ref+ > v ref- . 4 2 ain+ positive analog input. positive side of fully differential analog input. bypass ain+ to gnd with a 0.1f or greater capacitor. 5 3 ain- negative analog input. negative side of fully differential analog input. bypass ain- to gnd with a 0.1f or greater capacitor. 64i set segment current controller. connect to ground through a resistor to set the segment current. see table 6 for segment current selection. 7 5 gnd ground 8 v dd analog and digital circuit supply voltage. connect v dd to a +2.7v to +5.25v power supply. bypass v dd to gnd with a 0.1f and a 4.7f capacitor. 9 8 clk external clock input. when the extclk register bit is set to one, clk is the master clock input (frequency = 4.9152mhz) for the modulator and the filter. when the extclk register bit is reset to zero, the internal clock is used. connect clk to gnd or dv dd (max1499) or v dd (MAX1497) when the internal oscillator is used. 10 9 eoc active-low end-of-conversion logic output. a logic low at eoc indicates that a new adc result is available in the adc result register. 11 10 cs active-low chip select input. forcing cs low activates the serial interface. 12 11 din serial data input. data present at din is shifted into the internal registers in response to a rising edge at sclk when cs is low. 13 12 sclk serial clock input. apply an external clock to sclk to facilitate communication through the serial bus. sclk may idle high or low. 14 13 dout serial data output. dout presets serial data in response to register queries. data shifts out on the falling edge of sclk. dout goes high impedance when cs is high. 15 14 dig0 digit 0 driver 16 15 dig1 digit 1 driver 17 16 gled ground for led-display segment driver 18 17 dig2 digit 2 driver 19 18 dig3 digit 3 driver 20 20 sega segment a driver 21 21 segb segment b driver 22 22 segc segment c driver 23 23 segd segment d driver 24 24 sege segment e driver MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 11 detailed description the MAX1497/max1499 low-power, highly integrated adcs with led drivers convert a 2v differential input voltage (one count is equal to 100v for the max1499 and 1mv for the MAX1497) with a sigma-delta adc and output the result to an led or c. an additional 200mv input range (one count is equal to 10v for the max1499 and 100v for the MAX1497) is available to measure small signals with increased resolution. the devices operate from a single 2.7v to 5.25v power supply and offer 3.5-digit (MAX1497) or 4.5-digit (max1499) conversion results. an internal 2.048v refer- ence, internal charge pump, and a high-accuracy on- chip oscillator eliminate external components. the MAX1497/max1499 interface with a c using an spi-/qspi-/microwire-compatible serial interface. data can either be sent directly to the display or to the c first for processing before being displayed. the devices also feature on-chip buffers for the differ- ential input signal and external reference inputs, allow- ing direct interface with high-impedance signal sources. in addition, they use continuous internal offset- calibration and offer >100db of 50hz and 60hz line noise rejection. other features include data hold and peak detection, overrange and underrange detection. the max1499 also provides a low-battery monitor. analog input protection internal protection diodes limit the analog input range from vneg to (av dd + 0.3v) for the max1499, and from vneg to (v dd to 0.3v) for the MAX1497. if the analog input exceeds this range, limit the input current to 10ma. internal analog input/reference buffers the MAX1497/max1499 analog input/reference buffers allow the use of high-impedance signal sources. the input buffers common-mode input range allows the ana- log inputs and the reference to range from -2.2v to +2.2v. modulator the MAX1497/max1499 perform analog-to-digital con- versions using a single-bit, 3rd-order, sigma-delta mod- ulator. the sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. the modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input. the MAX1497/max1499 modulator provides 3rd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. the modulator is fully dif- ferential for maximum signal-to-noise ratio and mini- mum susceptibility to power-supply noise. a single-bit data stream is then presented to the digital filter to remove the frequency-shaped quantization noise. pin description (continued) pin MAX1497 max1499 name function 25 25 vled led-display segment-driver supply. connect to a +2.7v to +5.25v supply. bypass with a 0.1f capacitor to gled. 26 26 segf segment f driver 27 27 segg segment g driver 28 28 segdp segment dp driver 6av dd analog positive supply voltage. connect av dd to a +2.7v to +5.25v power supply. bypass av dd to gnd with a 0.1f capacitor. 7dv dd digital positive supply voltage. connect dv dd to a +2.7v to +5.25v power supply. bypass dv dd to gnd with a 0.1f capacitor. 19 dig4 digit 4 driver 29 led_en active-high led enable. the max1499 led display driver turns off when led_en is driven to logic low. the max1499 led display driver turns on when led_en is driven to logic high. 30 lowbatt low-battery voltage monitor. when the lowbatt input voltage is lower than 2.048v, the lowbatt bit in the status register is set to one. MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 12 ______________________________________________________________________________________ digital filtering the MAX1497/max1499 contain an on-chip digital low- pass filter that processes the data stream from the modulator using a sinc 4 response: the sinc 4 filter has a settling time of four output data periods (4 x 200ms). the MAX1497/max1499 have 25% overrange capabili- ty built into the modulator and digital filter. the digital fil- ter is optimized for the f clk equal to 4.9152mhz. other clock frequencies can be used; however, 50hz/60hz noise rejection decreases. the frequency response of the sinc 4 filter is calculated as follows: where n is the oversampling ratio, and f m = n x output data rate = 5hz. filter characteristics figure 2 shows the filter frequency response. the sinc 4 characteristic -3db cutoff frequency is 0.228 times the first notch frequency (5hz). the oversampling ratio (osr) for the MAX1497 is 128 and the osr for the max1499 is 1024. the output data rate for the digital filter corresponds to the positioning of the first notch of the filter s frequency response. the notches of the sinc 4 filter are repeated at multiples of the first notch frequency. the sinc 4 filter provides an attenuation of better than 100db at these notches. for example, 50hz is equal to 10 times the first notch frequency and 60hz is equal to 12 times the first notch frequency. for large step changes at the input, allow a settling time of 800ms before valid data is read. clock modes configure the MAX1497/max1499 to use either the internal oscillator or an externally applied clock to drive the modulator and filter. set the extclk bit in the con- trol register to zero to put the device in internal-clock mode. set the extclk bit to one to put the device in hz n z z hf n n f f f f n m m () () () () sin sin = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 4 4 - - - - sin( ) x x ? ? ? ? ? ? 4 max1499 binary-to- bcd converters adc led driver input buffers -2.5v ain+ ain- ref+ ref- +2.5v av dd dv dd gled 2.048v bandgap reference oscillator clock sclk din dout eoc seg1 segf segdp dig0 dig4 clk cs serial i/o and control +2.5v 2.048v gnd a = 1.22 to control charge pump -2.5v lowbatt v neg led_en vled i set figure 1. max1499 functional diagram MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 13 external-clock mode. when using the internal oscillator, connect clk to gnd or dv dd for the max1499, or con- nect clk to v dd for the MAX1497. the MAX1497/ max1499 ideally operate with a 4.9152mhz clock to achieve maximum rejection of 50hz/60hz common- mode, power-supply, and normal-mode noise. internal-clock mode the MAX1497/max1499 contain an internal oscillator. the power-up condition for the MAX1497/max1499 is internal clock operation with the extclk bit in the con- trol register equal to zero. using the internal oscillator saves board space by removing the need for an exter- nal clock source. external-clock mode for external clock operation, set the extclk bit in the control register to one and drive clk with a 4.9152mhz clock source for best 50hz/60hz rejection ratio. other external clock frequencies allow for custom conversion rates. a 2.4576mhz clock signal reduces the conver- sion rate and the led update rate by a factor of two while keeping good 50hz/60hz noise rejection. the MAX1497/max1499 operate with an external clock source of up to 5.05mhz. charge pump the MAX1497/max1499 contain an internal charge pump to provide the negative supply voltage for the internal analog input/reference buffers. the bipolar input range of the analog input/reference buffers allows this device to accept negative inputs with high source impedances. connect a 0.1f capacitor from vneg to gnd. led driver the max1499 has a 4.5-digit common-cathode display driver and the MAX1497 has a 3.5-digit common-cath- ode display driver. figures 3 and 4 show the connection schemes for a standard seven-segment led display. the led update rate is 2.5hz. the MAX1497/ max1499 automatically display the results of the adc, if desired ( table 1 ). the MAX1497/max1499 also allow independent control of the led driver through the serial interface, allowing for data processing of the adc result before showing the result on the led. additionally, each led segment can be individually controlled (see the led segment-display register sections). a b c aaaa d digit 4 digit 3 digit 2 digit 1 digit 0 dddd e g f eee gggg f fff bbbb cc cc dp dp dp dp dp figure 3. segment connection for the max1499 (4.5 digits) a b aa a d digit 3 digit 2 digit 1 digit 0 ddd e g f ee ggg fff bbb cc c dp dp dp dp c figure 4. segment connection for the MAX1497 (3.5 digits) seg_sel spi/ adc hold peak display values form 1xxx led segment registers 01xx led display register (user written) 0 0 1 x led display register 0 0 0 1 peak register 0 0 0 0 adc result register table 1. led priority table x = don? care. frequency (hz) gain (db) 50 40 30 20 10 -160 -120 -80 -40 0 -200 060 figure 2. frequency response of the sinc 4 filter (notch at 60hz) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 14 ______________________________________________________________________________________ figure 5 shows a typical common-cathode configura- tion for two digits. in common-cathode configuration, the cathodes of all leds in a digit are connected together. each segment driver of the MAX1497/ max1499 connects to its corresponding leds anodes. for example, segment driver sega connects to all led segments designated as a. similar configurations are followed for other segment drivers. the MAX1497/max1499 use a multiplexing scheme to drive one digit at a time. the scan rate is fast enough to make the digits appear to be lit. figures 6 and 7 show data timing diagrams for the MAX1497/max1499 where t is the display scan period typically around 1/512hz or 1.9531ms for the max1499 and 1/640hz or 1.5625ms for the MAX1497. t on in figures 6 and 7 denotes the amount of time each digit is on and is calculated as follows: the MAX1497/max1499 allow for full decimal-point control and feature leading-zero suppression. use the dpon, dpset1, and dpset2 bits in the control register to set the value of the decimal point ( tables 2 and 3 ). the MAX1497/max1499 overrange and underrange display is shown in table 4. t tms s max t tms s max on on == = == = 5 1 95312 5 390 60 1499 4 1 5625 4 390 60 1497 . .( ) . .( ) a a a digit 1 digit 2 segdp segg segf sege segd segc segb sega dd ee gg ff bb cc dp dp b c d e f g dp a b c d e f g dp figure 5. two-digit common-cathode configuration table 2. decimal-point control table max1499 dpon dpset1 dpset2 display output zero input reading 0 0 0 18888 0 0 0 1 18888 0 0 1 0 18888 0 0 1 1 18888 0 1 0 0 1888.8 0.0 1 0 1 188.88 0.00 1 1 0 18.888 0.000 1 1 1 1.8888 0.0000 table 3. decimal-point control table MAX1497 dpon dpset1 dpset2 display output zero input reading x 0 0 188.8 0.0 x 0 1 18.88 0.00 x 1 0 1888 0 x 1 1 1.888 0.000 x = don? care. table 4. led during overrange and underrange conditions condition MAX1497 max1499 overrange 1 --- 1 ---- underrange - 1 --- - 1 ---- MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 15 leading-zero suppression the MAX1497/max1499 include a leading-zero sup- pression circuitry to turn off unnecessary zeros. for example, when dpset1 and dpset2 = [0,0], 0.0 is dis- played instead of 000.0. this feature saves a substan- tial amount of power from being wasted. interdigit blanking the MAX1497/max1499 also include an interdigit blanking circuitry. without this feature, it is possible to see a faint digit next to a digit that is completely on. the interdigit blanking circuitry prevents bleeding over into the next digit for a short period of time. the typical interdigit blanking time is 4s. reference the MAX1497/max1499 reference sets the full-scale range of the adc transfer function. with a nominal 2.048v reference, the adc full-scale range is 2v with the range bit equal to zero. with the range bit set to one, the full-scale range is 200mv. a decreased refer- ence voltage decreases full-scale range (see the transfer functions section). the MAX1497/max1499 accept either an external ref- erence or an internal reference. the intref bit selects the reference mode (see the control register (read/write) section). for internal reference operation, set the intref bit to one, connect ref- to gnd, and bypass ref+ to gnd with a 4.7f capacitor. the internal reference provides a nominal 2.048v source between ref+ and gnd. the internal reference temperature coefficient is typically 40ppm/ c. the default power-on state sets the MAX1497/ max1499 to use the external reference with the intref bit cleared to zero. the external reference inputs, ref+ and ref-, are fully differential. for a valid external refer- ence input, v ref+ must be greater than v ref- . bypass ref+ and ref- with a 0.1f or greater capacitor to gnd in external reference mode. figure 16 shows the MAX1497/max1499 operating with an external single-ended reference. in this mode, ref- is connected to gnd and ref+ is driven with an exter- nal 2.048v reference. bypass ref+ to gnd with a 0.47f capacitor. 1 43210432 04 t t on digit 4 (msd) digit 3 digit 2 digit 1 digit 0 (lsd) data msd lsd figure 6. led voltage waveform?ax1499 3 32103210 21 t t on digit 3 (msd) digit 2 digit 1 digit 0 (lsd) data msd lsd figure 7. led voltage waveform?ax1497 MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 16 ______________________________________________________________________________________ figure 15 shows the MAX1497/max1499 operating with an external differential reference. in this mode, ref- is connected to the top of the strain gauge and ref+ is connected to the midpoint of the resistor-divider of the supply. applications information serial interface the spi/qspi/microwire serial interface consists of a chip select ( cs ), a serial clock (sclk), a data in (din), a data out (dout), and an asynchronous eoc output. eoc provides an asynchronous end-of-conversion sig- nal with a period of 200ms (f clk = 4.9152mhz). the MAX1497 updates the data register when eoc goes high. data is valid in the adc result registers when eoc returns low. the serial interface provides access to 12 on-chip registers, allowing control to all the power modes and functional blocks. table 5 lists the address and read/write accessibility of all the registers. a logic high on cs tri-states dout and causes the MAX1497/max1499 to ignore any signals on sclk and din. to clock data in or out of the internal shift register, drive cs low. sclk synchronizes the data transfer. the rising edge of sclk clocks din into the shift register, and the falling edge of sclk clocks dout out of the shift register. din and dout are transferred msb first (data is left justified). figures 8 12 show the detailed serial interface timing diagrams for the 8- and 16-bit read/write operations. all communication with the MAX1497/max1499 begins with a command byte on din, where the first logic one on din is recognized as the start bit (msb) for the command byte. the following seven clock cycles load the command into a shift register. these 7 bits specify which of the registers are accessed next, and whether a read or write operation takes place. transitions on the serial clock after the command byte transfer, cause a write or read from the device until the correct number of cs sclk din dout t csh t cl t ds t dh t dv t ch t do t tr t csh t css figure 8. detailed timing diagram sclk cs din dout 1 0 rs4 rs3 rs2 rs1 d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 rs0 x d15 d14 d13 d12 d11 d10 control byte data byte figure 9. serial-interface, 16-bit, write timing diagram MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 17 sclk cs din dout 1 1 rs4 rs3 rs2 rs1 rs0 x d7 d6 d5 d4 d3 d2 d1 d0 control byte data byte figure 12. serial-interface, 8-bit, read timing diagram cs sclk din dout 1 0 rs4 rs3 rs2 rs1 d7 d6 d5 d4 d3 d2 d1 d0 rs0 x control byte data byte figure 10. serial-interface, 8-bit, write timing diagram sclk cs din dout 1 1 rs4 rs3 rs2 rs1 rs0 x d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 d15 d14 d13 d12 d11 d10 control byte data byte figure 11. serial-interface, 16-bit, read timing diagram MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 18 ______________________________________________________________________________________ bits have been transferred (8 or 16). once this has occurred, the MAX1497/max1499 wait for the next command byte. cs must not go high between data transfers. if cs is toggled before the end of a write or read operation, the device mode may be unknown. clock in 32 zeros to clear the device state and reset the interface so it is ready to receive a new command byte. on-chip registers the MAX1497/max1499 contain 12 on-chip registers. these registers configure the various functions of the device and allow independent reading of the adc results and writing to the led display. table 5 lists the address and size of each register. the first of these registers is the status register. the 8- bit status register contains the status flags for the adc. the second register is the 16-bit control register. this register sets the led display controls, range modes, power-down modes, offset calibration, and the reset register function (clr). the third register is the 16-bit overrange register, which sets the overrange limit of the analog input. the fourth register is the 16-bit under- range register, which sets the underrange limit of the analog input. registers 5 through 7 contain the display data for the individual segments of the led. the eighth register contains the custom offset value. the ninth reg- ister contains the 16 msbs of the adc conversion result. the 10th register contains the led data. the 11th register contains the peak analog input value. the last register contains the lower four lsbs of the 20-bit adc conversion result. register n0. address rs [4:0] name width access 1 00000 status register 8 read only 2 00001 control register 16 r/ w 3 00010 overrange register 16 r/ w 4 00011 underrange register 16 r/ w 5 00100 led segment-display register 1 16 r/ w 6 00101 led segment-display register 2 16 r/ w 7 00110 led segment-display register 3 8 r/ w 8 00111 adc custom offset register 16 r/ w 9 01000 adc result register 1 (16 msbs) 16 read only 10 01001 led data register 16 r/ w 11 01010 peak register 16 read only 12 10100 adc result register 2 (4 lsbs) 8 read only all other addresses reserved table 5. register address table 6k ? 6k ? dout dout gnd gnd dv dd c load 50pf c load 50pf a) v oh to high-z b) v ol to high-z figure 13. load circuits for disable time 6k ? 6k ? dout dout gnd gnd dv dd c load 50pf c load 50pf b) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol figure 14. load circuits for enable time MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 19 default values: 00h this register contains the status of the conversion results. sign: latched negative-polarity indicator. latches high when the result is negative. clears by reading the status register, unless the condition remains true. over: overrange bit. latches high if an overrange condition occurs (the adc result is larger than the value in the overrange register). clears by reading the status register, unless the condition remains true. under: underrange bit. latches high if an under- range condition occurs (the adc result is less than the value in the underrange register). clears by reading the status register, unless the condition remains true. low_batt: low-battery bit. latches high if the volt- age at the lowbatt is lower than 2.048v (typ). clears by reading the status register, unless the condition remains true. for the MAX1497, lowbatt is not used and the lowbatt bit always returns to zero. drdy: data ready bit. latches high to indicate a com- pleted conversion result with valid data. read the adc result register to clear this bit. control and status registers command byte (write only) status register (read only) msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start(1) r/ w rs4 rs3 rs2 rs1 rs0 x msb lsb sign over under low_batt drdy 0 0 0 control register (read/write) msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 spi/ adc extclk intref dpon dpset2 dpset1 pd_dig pd_ana lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hold peak range clr seg_sel offset_cal1 offset_ cal2 enable start: start bit. the first 1 clocked into the MAX1497/ max1499 is the first bit of the command byte. (r/ w ): read/ write . set this bit to 1 to read from the specified register. set this bit to zero to write to the selected register. note that certain registers are read only. write commands to a read-only register are ignored. (rs4 rs0): register address bits. rs4 to rs0 specify which register is accessed. x: don t care. default values: 0000h this register is the primary control register for the MAX1497/max1499. it is a 16-bit read/write register. it is used to indicate the desired clock and reference source. it sets the led display controls, range modes, power-down modes, offset calibration, and the reset register function (clr). enable: (default = 1) led driver enable bit. when set to 1, the MAX1497/max1499 enables the led display dri- vers. a 0 in this location disables the led display drivers. offset_cal2: (default = 0) enhanced offset-calibra- tion start bit (max1499, range = 1). to achieve the lowest possible offset in the 200mv input range, per- form an enhanced offset calibration by setting this bit to MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 20 ______________________________________________________________________________________ 1. the calibration takes about nine cycles (1800ms). after the calibration completes, set this bit to zero to resume adc conversions. offset_cal1: (default = 0) automatic offset calibra- tion enable bit. when set to 1, the MAX1497/ max1499 disable automatic offset calibration. when this bit is set to zero, automatic offset calibration is enabled. seg_sel: (default = 0) seg_sel segment selection bit. when set to 1, the led segment drivers use the led segment registers to display individual segments that can form letters or numbers or other information on the display. the led data register is not displayed. send the data first to the led segment-display regis- ters and then set this bit high. clr: (default = 0) clear all registers bit. when set to 1, all registers reset to their power-on reset states after cs makes a low-to-high transition. range: (default = 0) input range select bit. when set to zero, the input voltage range is 2v. when set to 1, the input voltage range is 200mv. peak: (default = 0) peak bit. when set to 1 (and the hold bit is set to zero), the led shows the result stored in the peak register (see table 6). hold: (default = 0) hold bit. when set to 1, the led register does not update from the adc conversion results and holds the last result on the led. the MAX1497/max1499 continue to perform conversions during hold (table 1). pd_ana: (default = 0) power-down analog select bit. when set to 1, the analog circuits (analog modulator and adc input buffers) go into the power-down mode. when set to zero, the device is in full power-up mode. pd_dig: (default = 0) power-down digital select bit. when set to 1, the digital circuits (digital filter and led drivers) go into power-down mode. this also resets the values of the internal sram in the digital filter to zeros. when set to zero, the device returns to full power-up mode. when powering down pd_d1g, power down the led segment drivers by clearing the enable bit to zero. dpset[2:1]: (default = 00) decimal-point selection bits (table 2 and 3). dpon: (default = 0) decimal-point enable bit (tables 2 and 3). intref: (default = 0) reference select bit. for internal reference operation, set intref to 1. for external refer- ence operation, set intref to zero. extclk: (default = 0) external clock select bit. the extclk bit controls selection of the internal clock or an external clock source. a 1 in this location selects the signal at the clk input as the clock source. a zero in this location selects and powers up the internal clock oscillator. spi/ adc : (default = 0) display select bit. the spi/ adc bit controls selection of the data fed into led data register. a 1 in this location selects spi/qspi/ microwire data (user writes this data to the led data register). a zero in this location selects the adc result register data, unless hold or peak functions are active (table 1). note: when changing any one of the following control bits: offset_cal1 , range, pd_ana, pd_dig, intref, and extclk, wait 800ms before reading the adc results. overrange register (read/write) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default values: 7cf0h (for 3.5-digit, +1999) 4e1fh (for 4.5-digit, +19,999) the overrange register is a 16-bit read/write register (d15 is the msb). when the conversion result exceeds the value in the overrange register, the over bit in the status register latches to 1. the led shows a 1 followed by four dashes for the max1499 or a 1 followed by three dashes for the MAX1497 (table 4). the data is represented in two s complement format. MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 21 default values: 8300h (for 3.5-digit, -2000) b1e0h (for 4.5-digit, -20,000) the underrange data register is 16-bit read/write regis- ter (d15 is the msb). when the conversion result falls below the value in the underrange register, the undr bit in the status register sets to 1. the led shows a -1 followed by four dashes for the max1499 or a -1 fol- lowed by three dashes for the MAX1497 (table 4). the data is represented in two s complement format. default values: 0000h underrange register (read/write) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 led segment-display register 1 (read/write) msb bit 15 bit 14 bit 13 bit 1 bit 11 bit 10 bit 9 bit 8 a1 g1 d1 f1 e1 dp2 x b0 lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0 a0 g0 d0 f0 e0 dp1 0 led segment-display register 1 is a 16-bit read/write register. when the led bit (in the control register) is set to 1, the MAX1497/max1499 provide direct access to individual led segments. the bits in the led segment- display register determine if a segment is on or off. write a zero to turn on a segment and a 1 to turn off a segment. dp1 : segment dp driver bit of digit 1. the default value turns on the led segment. e0 : segment e driver bit of digit 0. the default value turns on the led segment. f0 : segment f driver bit of digit 0. the default value turns on the led segment. d0 : segment d driver bit of digit 0. the default value turns on the led segment. g0 : segment g driver bit of digit 0. the default value turns on the led segment. a0 : segment a driver bit of digit 0. the default value turns on the led segment. c0 : segment c driver bit of digit 0. the default value turns on the led segment. b0 : segment b driver bit of digit 0. the default value turns on the led segment. x: don t care. dp2 : segment dp driver bit of digit 2. the default value turns on the led segment. e1 : segment e driver bit of digit 1. the default value turns on the led segment. f1 : segment f driver bit of digit 1. the default value turns on the led segment. d1 : segment d driver bit of digit 1. the default value turns on the led segment. g1 : segment g driver bit of digit 1. the default value turns on the led segment. a1 : segment a driver bit of digit 1. the default value turns on the led segment. MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 22 ______________________________________________________________________________________ default values: 0000h led segment-display register 2 is a 16-bit read/write register. when the seg_sel bit (in the control register) is set to 1, the MAX1497/max1499 provide direct access to individual led segments. the bits in the led segment-display register determine if a segment is on or off. write a zero to turn on a segment and a 1 to turn off a segment. c1 : segment c driver bit of digit 1. the default value turns on the led segment. b1 : segment b driver bit of digit 1. the default value turns on the led segment. minus : segment minus driver bit. the default value turns on the led minus segment. setting this bit to 1 enables the plus sign on the led display. dp3 : segment dp driver bit of digit 3. the default value turns on the led segment. e2 : segment e driver bit of digit 2. the default value turns on the led segment. f2 : segment f driver bit of digit 2. the default value turns on the led segment. d2 : segment d driver bit of digit 2. the default value turns on the led segment. g2 : segment g driver bit of digit 2. the default value turns on the led segment. a2 : segment a driver bit of digit 2. the default value turns on the led segment. c2 : segment c driver bit of digit 2. the default value turns on the led segment. b2 : segment b driver bit of digit 2. the default value turns on the led segment. dp4 : segment dp driver bit of digit 4. the default value turns on the led segment (max1499 only). e3 : segment e driver bit of digit 3. the default value turns on the led segment (max1499 only). f3 : segment f driver bit of digit 3. the default value turns on the led segment (max1499 only). led segment-display register 2 (read/write) msb bit 15 bit 14 bit 13 bit 1 bit 11 bit 10 bit 9 bit 8 f3 e3 dp4 minus b2 c2 a2 g2 lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d2 f2 e2 dp3 x b1 c1 0 MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 23 default values: 0000h in addition to automatic offset calibration, the MAX1497/max1499 offer a user-defined custom offset 16-bit read/write register. the final result of the adc conversion is the input after autocalibration minus the value in the custom offset. the custom offset value is stored in this register. d15 is the msb. the data is represented in two s complement format. adc custom offset-calibration register (read/write) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 adc result register 1 (read only) msb lsb (MAX1497) lsb (max1499) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default values: 0000h adc result register 1 is a 16-bit read-only register. this register stores the 16 msbs of the adc result. the data is represented in two s complement format. for the max1499, the data is 16-bit and d15 is the msb. for the MAX1497, the data is 12-bit, d15 is the msb, and d4 is the lsb. led segment-display register 3 (read/write) msb lsb xx bc_ b3 c3 a3 g3 d3 default values: 00h led segment-display register 3 is an 8-bit read/write register. when the seg_sel bit (in the control register) is set to 1, the MAX1497/max1499 provide direct access to individual led segments. the bits in the led segment-display register determine if a segment is on or off. write a zero to turn on a segment and a 1 to turn off a segment. d3 : segment d driver bit of digit 3. the default value turns on the led segment (max1499 only). g3 : segment g driver bit of digit 3. the default value turns on the led segment (max1499 only). a3 : segment a driver bit of digit 3. the default value turns on the led segment (max1499 only). c3 : segment c driver bit of digit 3. the default value turns on the led segment (max1499 only). b3 : segment b driver bit of digit 3. the default value turns on the led segment (max1499 only). bc_ : segment b and c driver bit of digit 3 (3.5 digits) or digit 4 (4.5 digits). the default value turns on the led segment. x: don t care. MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 24 ______________________________________________________________________________________ peak register (read only) msb lsb (MAX1497) lsb (max1499) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default values: 0000h the led data register is a 16-bit read/write register. this register updates from adc result register 1 or from the serial interface by selecting the spi/ adc bit in the control register. the data is represented in two s com- plement format. for the max1499, the data is 16-bit and d15 is the msb. for the MAX1497, the data is 12-bit, d15 is the msb, and d4 is the lsb, followed by 4 trailing sub-bits. default values: b1e0h the peak data register is a 16-bit read only register. set the peak bit to 1 to enable the peak function. this reg- ister stores the peak value of the adc conversion result. first, the current adc result is saved to the peak register, then the new adc conversion result is compared to this value. if the new value is larger than the value in the peak register, the MAX1497/max1499 save the new value to the peak register. if the new value is less than the value in the peak register, the value in the peak register remains unchanged. set the peak bit to zero to clear the value in the peak register. the data is represented in two s complement format. for the max1499, the data is 16-bit and d15 is the msb. for the MAX1497, the data is 12-bit, d15 is the msb, and d4 is the lsb followed by 4 trailing sub-bits. led data register (read/write) msb lsb (MAX1497) lsb (max1499) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 adc result register 2 (read only) msb lsb d3 d2 d1 d0 0 0 0 0 default values: 00h adc result register 2 is an 8-bit read-only register. this register stores the 4 lsbs of the adc result. use this result with the result in adc result-register 1 to form a 20-bit two s complement conversion result. MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 25 default values: b1e0h the peak data register is a 16-bit read only register. set the peak bit to 1 to enable the peak function. this reg- ister stores the peak value of the adc conversion result. first, the current adc result is saved to the peak register, then the new adc conversion result is compared to this value. if the new value is larger than the value in the peak register, the MAX1497/max1499 save the new value to the peak register. if the new value is less than the value in the peak register, the value in the peak register remains unchanged. set the peak bit to zero to clear the value in the peak register. the data is represented in two s complement format. for the max1499, the data is 16-bit and d15 is the msb. for the MAX1497, the data is 12-bit, d15 is the msb, and d4 is the lsb followed by 4 trailing sub-bits. power-on reset at power-on, the serial interface, logic led drivers, dig- ital filter, and modulator circuits reset. the registers return to their default values. allow time for the refer- ence to settle before starting calibration. offset calibration the MAX1497/max1499 offer on-chip offset calibration. the device offset calibrates during every conversion when the offset_cal1 bit is zero in the control regis- ter. enhanced offset calibration is only needed in the max1499 when the range bit = 1. it is performed on demand by setting the offset_cal2 bit to 1. enhanced offset calibration enhanced offset calibration is a more accurate calibra- tion method that is needed in the case of the 200mv range and 4.5-digit resolution. the max1499 performs the enhanced calibration on demand by setting the offset_cal2 bit to 1. power-down modes the MAX1497/max1499 feature independent power- down control of the analog and digital led drivers cir- cuitry. writing a 1 to the pd_dig and pd_ana bits in the control word, powers down the analog and digital circuitry, reducing the supply current to 268a (typ). pd_dig powers down the digital filter, while pd_ana powers down the analog modulator and adc input buffers. writing a zero to the enable bit in the control word, powers down the led drivers. peak the MAX1497/max1499 feature peak detection circuit- ry. when activated (peak bit = 1), the devices display only the highest voltage measured to the led. figure 16. thermocouple application with the MAX1497/max1499 figure 15. strain-gauge application with the MAX1497/max1499 MAX1497 max1499 av dd dv dd dout din sclk 4.7 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f analog supply ferrite bead r ref r r active gauge dummy gauge ref+ ref- ain+ ain- gnd eoc cs 4.7 f 0.1 f MAX1497 max1499 max6062 +5v +2.048v temp sensor thermocouple junction 0.1 f 0.47 f spi c ain+ ain- ref+ ref- gnd MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 26 ______________________________________________________________________________________ hold the MAX1497/max1499 feature data-hold circuitry. when activated (hold bit = 1), the device displays the current reading on the led. low battery the max1499 features a low-battery detection input. when the voltage at lowbatt drops below 2.048v (typ), the lowbatt bit of the status register goes high. strain-gauge measurement connect the differential inputs of the MAX1497/max1499 to the bridge network of the strain gauge. in figure 15 , the analog supply voltage powers the bridge network and the MAX1497/max1499 along with the reference voltage. the MAX1497/max1499 handle an analog input voltage range of 200mv and 2v full scale. the ana- log/reference inputs of the parts allow the analog input range to have an absolute value of anywhere between -2.2v and +2.2v. thermocouple measurement figure 16 shows a connection from a thermocouple to the MAX1497/max1499. in this application, the MAX1497/max1499 take advantage of the on-chip input buffers that allow large source impedances on the front end. the decoupling capacitors reduce noise pickup from the thermocouple leads. to place the dif- ferential voltage from the thermocouple at a suitable common-mode voltage, the ain- input of the MAX1497/ max1499 is biased to gnd. use an external tempera- ture sensor, such as the ds75, and a c to perform cold-junction temperature compensation. transfer functions figures 17 20 show the transfer functions of the MAX1497/max1499. the output data is stored in the adc data register in two s complement. the transfer function for the max1499 with ain+ - ain- 0, range = 0 is: the transfer function for the max1499 with ain+ - ain- < 0, range = 0 is: the transfer function for the MAX1497 with ain+ - ain- 0, range = 0 is: the transfer function for the MAX1497 with ain+ - ain- < 0, range = 0 is: counts vv vv ain ain ref ref . = ? ? ? ? ? ? + ? + ? ? ? 1 024 2000 counts vv vv ain ain ref ref . , = ? ? ? ? ? ? + + + ? ? ? ? 1 024 20 000 1 counts vv vv ain ain ref ref . , = ? ? ? ? ? ? + + ? ? ? ? 1 024 20 000 >4e1fh 4e1fh 0002h 0001h 0000h ffffh fffeh fffdh b1e0h MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 28 ______________________________________________________________________________________ possible with double-sided boards. with this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is important when using high-resolution adcs. decouple the supplies with 0.1f ceramic capaci- tors to gnd. place these components as close to the device as possible to achieve the best decoupling. segment-current selection a resistor from iset to ground sets the current for each led segment. see table 6 for more detail. use the fol- lowing formula to set the segment current: r iset values below 25k ? increase the i seg . however, the internal current-limit circuit limits the i seg to less than 30ma. at higher i seg values, the proper operation of the device is not guaranteed. in addition, the power dissipat- ed may exceed the package power dissipation limit. choosing supply voltage to minimize power dissipation the MAX1497/max1499 drive a peak current of 25.5ma into leds with a 2.2v forward-voltage drop when operated from a supply voltage of at least 3.0v. therefore, the minimum voltage drop across the inter- nal led drivers is (3.0v - 2.2v) = 0.8v. the MAX1497/ max1499 sink (8 x 25.5ma = 204ma) when the outputs are operating and led segment drivers are at full cur- rent. for a 3.3v supply, the MAX1497/max1499 dissi- pate (3.3v - 2.2v) x 204 = 224.4mw. if a higher supply voltage is used, the driver absorbs a higher voltage, and the driver s power dissipation increases according- ly. however, if the leds used have a higher forward voltage drop than 2.2v, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.8v headroom. for a vled supply voltage of 2.7v, the maximum led forward voltage is 1.9v to ensure 0.8v driver headroom. the voltage drop across the drivers with a nominal +5v supply (5.0v - 2.2v = 2.8v) is almost three times the drop across the drivers with a nominal 3.3v supply (3.3v - 2.2v = 1.1v). therefore, the driver s power dissi- pation increases three times. the power dissipation in the part causes the junction temperature to rise accord- ingly. in the high ambient temperature case, the total junction temperature may be very high (>+125 c). at higher junction temperatures, the adc performance degrades. to ensure the dissipation limit for the MAX1497/max1499 is not exceeded and the adc per- formance is not degraded, a diode can be inserted between the power supply and vled. computing power dissipation the following can be used to compute power dissipa- tion: pd = (vled x i vled ) + (vled - v diode ) (duty x i seg x n) + v supply x i supply vled = led driver supply voltage i vled = vled bias current v diode = led forward voltage duty = segment on time during each digit on time i seg = segment current set by r iset n = number of segments driven (worst case is eight) v supply = supply voltage of the part i supply = supply current from v dd for the MAX1497 or av dd + dv dd for the max1499 dissipation example for i seg = 25.5ma, n = 8, duty = 127 / 128, v diode = 1.5v at 25.5ma, vled = v supply = 5.25v: pd = (5.25 x 2ma) + (5.25v - 1.5) [(127 / 128) x 25.5ma x 8)] + 5.25 x 1.080ma pd = 0.7751w 28-pin ssop package example for the 28-pin ssop package (tja = 1 / 0.009496 = +105.3 c/w), the maximum allowed ambient tempera- ture t a is given by: tj (max) = t a + (pd x tja) = +125 c = t a + (0.7751w x +105.3 c/w) t a = +43 c thus, the device cannot operate safely at a maximum package temperature of +85 c. the power dissipates in the part need to be lowered. (pd x tja) max = (+125 c) - (+85 c) = +40 c pd (max) = +40 c /+105.3 c/w = 380mw (vled - v diode ) = [380mw - (5.25v x 2ma) - 5.25v x 1.080ma] / [(127 / 128) x 25.5ma x 8] vled - v diode = 1.854v vled - v diode should have the following condition to ensure it operates safely: 0.8v < vled - v diode < 2.08v 28-pin pdip package example pd x tja (max) = (+125 c) - (+85 c) = +40 c pd (max) = +40 c /+70 c/w = 571mw i v r seg iset = ? ? ? ? ? ? 120 450 . MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 29 vled - v diode = [571mw - (5.25v x 2ma) - 5.25v x 1.080ma] / [(127 / 128) x 25.5ma x 8] vled - v diode = 2.80v for a 28-pin pdip package, vled - v diode should have the following condition to ensure it operates safe- ly: 0.8v < vled - v diode < 3.18v 32-pin tqfp package the max1499 tqfp package can operate safely for all supply voltages provided v diode > 1.5v. definitions inl integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the MAX1497/max1499 is measured using the end- point method. dnl differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. rollover error rollover error is defined as the absolute-value differ- ence between a near positive full-scale reading and near negative full-scale reading. rollover error is tested by applying a full-scale positive voltage, swapping ain+ and ain-, and adding the results. zero input reading ideally, with ain+ connected to ain-, the MAX1497/ max1499 digital adc result is 0000h. zero input read- ing is the measured deviation from the ideal 0x0000 and the actual measured point. gain error gain error is the amount of deviation between the mea- sured full-scale transition point and the ideal full-scale transition point. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 segdp segg segf vled sege segd dig0 segc segb sega dig3 dig2 gled dig1 dout sclk din cs eoc clk v dd gnd ain- ain+ i set ref+ ref- vneg ssop/pdip top view MAX1497 top view max1499 tqfp 32 28 29 30 31 25 26 27 v neg lowbatt led_en segdp ref- segg segf vled 10 13 15 14 16 11 12 9 din dout sclk dig1 dig0 gled 17 18 19 20 21 22 23 segd 24 sege segc segb sega dig4 dig3 dig2 2 3 4 5 6 7 8 clk dv dd av dd gnd i set ain- ain+ 1 ref+ cs eoc pin configurations MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 30 ______________________________________________________________________________________ MAX1497 0.1 f 4.7 f c 0.1 f 10 f 2.7v to 5.25v ain+ ain- vled v dd i set v neg gnd ref- ref+ gled clk sclk din dout cs eoc dig0?ig3 digit connections sega?egdp segment connections v in 25k ? typical operating circuits max1499 0.1 f 4.7 f c 0.1 f 0.1 f 10 f 10 f l iso 2.7v to 5.25v ain+ ain- vled dv dd av dd i set v neg gnd ref- ref+ gled clk sclk din dout cs eoc dig0 dig4 digit connections sega segdp segment connections v in lowbatt 25k ? MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface ______________________________________________________________________________________ 31 32l/48l,tqfp.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface 32 ______________________________________________________________________________________ ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) MAX1497/max1499 3.5- and 4.5-digit, single-chip adcs with led drivers and c interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. pdipw.eps package outline, .600" pdip 1 1 21-0044 b rev. document control no. approval proprietary information title: top view front view 0.700 max - 0.200 0.020 0.080 0.009 0.625 0.012 0.065 0.600 bsc inches e1 - ea eb 0.005 0.600 0.008 d1 e c dim 0.045 0.016 0.055 0.015 b b1 a1 a3 min - a 15.24 bsc - 0.13 0.21 15.24 17.78 0.22 15.87 0.30 millimeters 0.39 0.41 1.40 1.14 - min 0.51 1.65 - 2.03 max 5.08 a2 0.125 0.175 3.18 4.45 0.525 0.575 13.34 14.61 e 0.100 bsc 2.54 bsc 0.150 0.120 l 3.05 3.81 2.075 2.025 d d min dim d inches max 51.44 52.71 millimeters min max 40 ac 1.430 1.470 ab 37.34 36.32 28 1.230 1.270 aa 32.26 31.24 24 n ms011 n d a l a1 e b b1 a2 a3 e1 e c ea eb 0-15 side view 1 d1 variations: package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) |
Price & Availability of MAX1497
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |